Multiply and Accumulate Unit using Vedic Multiplier

Multiply and Accumulate Unit employ Vedic multiplier conceptionandImplementationofFPGA base64 microchipMA Cunit exploitationVEDICMultiplierandReversible system of logical systemgatesABSTRACTNow a days in VLSI technology size, power, and speed argon the main constraints to rule any circuits. In normal multiplier factors delay provide be more and the number of computations also will be more. Be manage of that speed of the circuits initiationed with the normal multipliers will be low and it will consume more power.This paper describes Multiply and Accumulate Unit utilise Vedic Multiplier and DKG reversible system of logic gates. The Vedic multiplier is intentional by using Urdhava Triyagbhayam sutra and the common viper traffic pattern is done by using reversible logic to perform highspeed operations. Reversible logic gates atomic number 18 also theessential constraint for the promising field of Quantum computing. The Urdhava Triyagbhayam multiplier is utilise for the mult iplication function to reduce partial reapings in the multiplication process and to get high concert and less bea .The reversible logic is used to get less power. The mac is designed using Verilog code, simulation,synthesis is done in both RTL compiler using Xilinx and implemented on Spartan 3e FPGA Board.KeyWordsMAC, Vedic multiplier, Reversible aditsI. INTRODUCTIONMultiplication is the key in arithmetic operation and multiplier plays an important role in digital signal Processing. Unfortunately, the major source of power dissipation in digital signal processors is multipliers. In the past decade researchers developed multipliers with the help of CMOS logic which has all(a) the disadvantages as discussed earlier. therefrom multipliers design for digital signal processing applications should be workmanlike. So the proposed method is designed using attain logic dominions, which shows improvements over CMOS designs. fountainhead logic principle based circuits are capable t o accomplish superior performance in power, speed and area when implemented in VLSI1. Several case studies show that pass logic principle based design implements most functions with fewer electronic transistors which reduces the overall capacitance than static CMOS thus, resulting in low power and fast switching time. The Pass logicstandard based design is a capable, due to its better performance in power consumption, area and speed.thirty percent of the multiplier blank shell is taken by the Booth encoder and selector logic 1-3. So a improved design of Booth encoder and selector is essential. The main objective of this work is to design and implement new Booth encoders and selector logics which are hardware efficient and consequently power- aware.Various designs of these logic units are proposed in this work where the number of transistors needed are less when compared to previously designed units.The gate level implementations of these designs were tested for functionality using LoKon software gates (XNOR, XOR , NAND,NOR,AND,XOR-XNOR combination gate) and MUX used in these circuits were simulated and verified for functionality using TopSPICE. Due to the limitation in the numbers of transistor count in the TopSPICE, it was not capable to simulate the entire circuit in the transistor level. Further, these designs were used to build multiplier2.Multiplier is the need for higher word width for signal process applications. This design is scalable without any loss of merits. All the pass transistor circuits have been tested for fully restored voltage at the output3. Therefore, when these circuits are combined to form the whole multiplier voltage drop will not cause a problem.II. LITERATURE REVIEWNareshnaik, SivaNagendra Reddy proposed programme of Vedic Multiplier for Digital Signal Processing Applications1 .In this method design of common vipers is difficult and design may be complex and also its require more power.Anitha, Sarath Kumar proposed A 32 BIT MAC Uni t Design Using Vedic Multiplier and Reversible Logic Gate design.In this paper they designed for 32 bit Multiplier.But most of the multipliers used in Digital signal processing applications 64 bit multipliers.So some(prenominal) researchers proposed many methods to design multipliers and adders.Among all the methods multiplier design with reversible logic gate design is the efficient method.In reversible gates also different reversible gate are available4.Some researchers used Kogge stone Adders,some one used Toffiligates5.DKG is the one of the gate used in the MAC design.This proposed method represents 64 bit MAC design using reversible logic gates.III. PROPOSEDMETHODMultiply Accumulate (MAC) unit is designed by using Multipliers and adders both will be joined by an accumulate unit. The applications of MAC unit are Digital Signal Processors, microprocessors, and logic units and.MAC determines the speed and improves the performance of the entire system6. The proficient designs by M AC unit are Fast Fourier Transform(FFT/IFFT) ,Discrete Cosine Transform (DCT). Since, they are normally executed by inflexible application of multiplication and addition, the total system speed and performance depends on the speed of the addition and multiplication process speed in the system7. In most cases the delay in the architecture is due to the addition in gibe stages which we have to concentrate more to improve the speed. Finally we are going to compare our Vedic MAC unit with the Conventional MAC unit based on the parameters like Speed,area and power consumption8.A multiplying blockfunction can be conceded in threedifferent ways naturalized addition, partial product addition (PPA) and nettly partial product Generation (PPG). The 2 bud vase materials that must be considered are raising the speed of MAC which is accumulator block partial and product reduction9. The 64 bit MAC design which will make use of Vedic multiplier and reversible logic gate can be accomplished in dickens stages. Firstly, multiplier stage, where a usual multiplier is replaced by Vedic multiplier using UrdhavaTriyagbhayam sutra from Vedic Mathematics.Multiplication is the primary operation of MAC unit. Speed, area, Power dissipation, consumptionand latency are the major concerns in the multiplier stage. So, to evade them, we will go for fast multipliers in different applications of DSP, ne iirking, and so forth There are mostly two major criterions that can possibly improve speed of the MAC units are sinking the partial products and because of that accumulator yoke is getting decreased. To perform the multiplication of N*N it requires approximately 2N-1 cross products of different widths and (log2N + 1) partial products. The partial products are obtained from Urdhava sutra is by Criss Cross Method. The maximum number of bits in partial products will lead to precise path. The second part of MAC is Reversible logic gate. Loss of every bit of information in the computations that are not reversible is kT*log2 joules of heat readiness are generated, where k is Boltzmanns constant and T the absolute temperature at which computation is performed.IV. DESIGN OF MAC ARCHITECTUREFig 1 MAC ArchitectureThe design of MAC architecture consists of 3 sub designs.Design of 64 X 64 bit Vedic Multiplier.Design of 128 bit DKG adderDesign of Accumulator which integrates both multiplier and adder stages.Vedic MultiplierVedic Mathematics is part of four Vedas(books of wisdom). It is part of Sthapatya- Veda (book on civil engineering and architecture), which is an upa- veda (supplement) of Atharva Veda.Vedic Mathematics existed in ancient India and was revived by a popular mathematician, Sri Bharati Krishna Tirthaji. He divided Vedic mathematics into sixteen formulae(sutras). These formulae deal with Algebra, Analytical Geometry, Algebra, Trigonometry, Geometry etc. The ease in the Vedic mathematics sutras covers way for its application in several prominent domains of engineer ing like Signal Processing, VLSI and Control Engineering .1) (Anurupye) Shunyamanyat2) ChalanaKalanabyham3) EkadhikinaPurvena4) EkanyunenaPurvena5) Gunakasamuchyah6) Gunitasamuchyah7) NikhilamNavatashcaramamDashatah8) ParaavartyaYojayet9) Puranapuranabyham10) Sankalana- vyavakalanabhyam11) ShesanyankenaCharamena12) ShunyamSaamyasamuccaye13) Sopaantyadvayamantyam14) Urdhva-tiryakbhyam15) Vyashtisamanstih16) YaavadunamVedic Maths can be divided into sixteen different sutras to perform mathematical operations. Among these surtras the Urdhwa Tiryakbhyam Sutra is one of the most highly preferred algorithmic rules for performing multiplication11-14. The algorithm is competent enough to be employed for the multiplication of integers as well as binary numbers. The term UrdhwaTiryakbhyam originated from 2Sanskrit words Urdhwa and Tiryakbhyam which mean vertically and crosswise respectively.The mainadvantage of utilizing this algorithm in comparison with the existing multiplication technique s, is the fact that it utilizes unless logical AND operations, half adders and full adders to complete the multiplication operation. Also, the partial products required for multiplication are generated in parallel and apriority to the actual addition thus saving a lot of processing time15-17.UrdhwaTiryakbhyam AlgorithmLet us consider two cardinal bit numbers X(70) and Y(70) , where 7 signify Most Significant Bit and 0 represent Least Significant Bit. P0 to P15 signify each bit of the final computed product. It can be seen from equation (1) to (15), that P0 to P15 are calculated by adding partial products, which are calculated previously using the logical AND operation.The individual bits obtained from equations (1) to equation (15), in turn when concatenated produce the final product of multiplication which is represent in equation (16).The carry bits generated during the computation of the individual bits of the final product are represented from C(1) to C(30). The carry bits ge nerated in (14) and (15) are ignored since they are redundant.Fig 2 Pictorial Illustration of UrdhwaTiryakbhyamSutraGraphically exemplifies the step by step procedure of multiplying two eight bit numbers using the Urdhwa Tiryakbyam Vedic Multiplication Sutra20. The black circles specify the bits of the multiplier and multiplicand, and the two-way arrows specify the bits to be multiplied in grade to arrive at theindividual bits of the final product. The hardware architecture of the 88 Urdhwa multiplier has been designed and shown in Fig 2. Lowest quantum costDKG GateA 4 X 4 reversible DKG gate that preservework singly as a reversible full adder and parallel adder is shown in below fig 5. If input A is zero, the DKG gate performed Full adder operation, and if input A is 1 thus reversible logic gate performed Full subtractor operation. It has been confirmed that a reversible full- adder circuit requires at least two or three scraps outputs to make the distinctive1019.output combin ationsFig 3 32 -32 Vedic multiplier using 16 - 16 Vedic multiplierFig 4 64- 64 Vedic multiplier using 32x32Vedic multiplierV. DESIGN OF ADDERUSINGFig. 5a DKG gateFig. 5b Parallel adder using DKG gateAccumulatorStageAccumulator has an important role in the DSPapplications in different ranges. The register designedREVERSIBLE LOGICDKGGATEin the accumulator is usedto add the multipliedReversible logic is a distinct method diverse from other logic). Loss of information is not probablenumbers. Multiplier, adder and an accumulator areforming the vital establishment for the MAC unit. The conventional MAC unit has a multiplic and and here. In this logic, the numbers of outputs are identical multiplier to do the basic multiplication and some to the number of inputs.General friendliness for reversible logicgateparallel adders to add the partial products generated inthe previous step. To get the final multiplication output A Boolean function is reversible if and only ifwe add the partial prod uct to these results. Vedic all the values in the input set can be mapped with a single value in the output position. Landauer and Multiplier has put forward to intensify the action of the MAC Unit.Bennet both demonstrated that conventional irreversible circuits willthe usage of take a shit us toVI. RESULTS AND DISCUSSIONpower dissipation a circuit consisting of only reversible gates does not dissipate power. The following points necessity be reticent in mind to realize an optimized circuit Loops are not authorized Minimum delay Zero energy dissipationFig 6 RTL conventional of MAC Unit Fan-out is not authorizedThe modified 64 bitmultiplier using Vedic Garbage outputs must be smallmultiplier and DKG adder is fast and design of MAC done using Xilinx.The above fig 7shows comparison between Verilog code using Xilinx. The below fig 6 shows theRTL Schematic of the proposed design.Logic Utilization70000No.of Slice FlipFlops60000No.of 4 input LUTs50000MAC design unit using different Adde rs. The number of LUTs and utilization of logic blocks in MAC design using CSA, RCA, KSA will be greater than DKG and speed is also more in MAC design using DKG. But it will take more area.Compare to array multipliers, baugh wooley multipliers and booths multipliers Vedic multipliers requires less area and performs operations at high speed.The below fig 8 shows the statistics results ofMAC design Vedic Multiplier with different adders. In which DKG Adders has moderate delay. But it consumes very less power and it can be designed in small area.40000 way out of occupiedSlices quash of Slices containing only related logic c0900800300002000010000Number of Slices containing unrelated logicTotal Number of 4 input LUTsNumber used as logicNumber used as ShiftRegisters700600500400300200100MAC Design using RCAMAC Design using CSAMAC Design using KSAMAC Design using DKG0Number of nonded0 IOBsNumber ofBUFGMUXsAverage Fanout of non-Clock NetsFig7 Synthesis report of 64-bit MAC using Vedic Multip lier using RCA,DKG and KSA Reversible logic gatesFig8 Delay compend report of 64-bit MAC using Vedic Multiplier using RCA,DKG and KSA Reversible logic gatesin table 2. By Combining the Vedic and reversible logic will direct to new and competent attainments in developing various fields of digital signal processing Applications.Fig 9 dissembling result of AdderThe above fig 9 shows that simulation result of DKG adder. It is a 32 bit adder. In this design we used two 64 bit adders. This adder has two inputs a and b,two outputs sum and carry. For adder a =19997091 and b= 0001fffdapplied.Which results sum is0199b708e and carry is 0.Fig 10 Vedic Multiplier result of 64 bit MAC unitThe above fig 10 shows the simulation result of 64 bit MAC design unit. For this design we applied two inputs. In which values are a=12345678 and b=78945612 and it will give result of55bed11b057ec60.Fig 11 Vedic Multiplier result of 64 bit MAC unit onFPGACONCLUSION AND FUTURE SCOPEThe results of this proposed 64 bit UrdhavaTriyagbhayam Vedic multiplier with DKG adder are quite good. Design of MAC unit structure and its performance has been scrutinize for all the blocks. Therefore, the 64-bit Urdhava Triyagbhayam sutra Multiplier and reversible logic is the best in all aspects like speed power product ,delay, area and complicationas compared to all other architectures which are shown